42. What is the return value of f(p,p) ,if the value of p is initialized to 5
before the call? Note that the first parameter is passed by reference, whereas
the second parameter is passed by value.
int f (int &x, int c) {
c=c-1;
if (c==0) return 1;
x=x+1;
return f(x,c) * x;
}
a) 3024
b) 6561
c) 55440
d) 161051
Answer: b
43. The preorder traversal
sequence of a binary search tree is 30, 20, 10, 15, 25, 23, 39, 35, 42. Which
one of the following is the postorder traversal sequence of the same tree?
a)
10,20,15,23,25,35,42,39,30
b)
15,10,25,23,20,42,35,39,30
c)
15,20,10,23,25,42,35,39,30
d)
15,10,23,25,20,35,42,39,30
Answer: d
44. Consider the following operation along with
Enqueue and Dequeue operations on queues, where k is a global parameter
MultiDequeue(Q) {
M=k
While( Q is not empty)
and (m >0) {
Dequeue(Q)
m=m-1
}
}
What is the worst case time complexity of a sequence
of n queue operations on an initially empty queue?
a) Θ(n)
b) Θ(n+k)
c) Θ(nk)
d) Θ(n 2)
Answer: c
45. Consider an instruction pipeline with five stages
without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI),
Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage
delays for FI, DI, FO, EI and WO are 5 ns, 7 ns, 10 ns, 8 ns and 6 ns,
respectively. There are intermediate storage buffers after each stage and the
delay of each buffer is 1 ns. A program consisting of 12 instructions I1 , I2 , I3 ,......I12 is executed in this pipelined processor. Instruction
I4 is the only branch
instruction and its branch target is I9 . If the branch is taken during the execution
of this program, the time (in ns) needed to complete the program is
a) 132
b) 165
c) 176
d) 328
Answer: a
46. A RAM chip has a capacity of 1024 words of 8 bits
each (1K
* 8) .
The number of 2 *4 decoders with enable line needed to construct a 16K *16 RAM
from 1K * 8 RAM is
a) 4
b) 5
c) 6
d) 7
Answer: d
47. Which one of the following is
NOT logically equivalent to ¬$x
("y (a) Ù
"z (b)) ?
a)
"x ($z
(¬b) ® "y (a))
b)
"x ("z
(b) ® $y (¬a))
c)
"x ("y
(a) ® $z (¬b))
d)
"x ($y
(¬a) ® $z (¬b))
Answer: a
Common data questions 48 and
49
The following code segment is executed on a processor
which allows only register operands in its instructions. Each instruction can
have almost two source operands and one destination operand. Assume that all
variables are dead after this code segment
c= a+ b;
d= c * a;
e= c+ a;
x= c * c;
if( x>a) {
y= a* a;
}
else {
d=d * d;
e=e * e;
}
48.
Suppose the instruction set architecture of the processor has only two
registers. The only allowed compiler optimization is code motion, which moves
statements from one place to another while preserving correctness. What is the
minimum number of spills to memory in the compiled code?
a)
0
b)
1
c)
2
d)
3
Answer: c
49.
What is the minimum number of registers
needed in the instruction set architecture of the processor to compile this
code segment without any spill to memory? Do not apply any optimization other
than optimizing register allocation
a) 3
b) 4
c) 5
d) 6
Answer: b
Next: Computer science and IT GATE 2013 answer key Questions 50-55
Previous: Computer science and IT GATE 2013 answer key Questions 37-41
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